嘉  宾

张于庆

Eugene Zhang is a Founding Partner of TSVC, a Silicon Valley-based venture capital firm focused on building and scaling early-stage technology startups. Eugene’s investment focus is emerging technologies and FinTech, and he has led investments in over 70 startups including Zoom, Carta, Gingko Bioworks.

Eugene has been working in the networking and computing industry for more than a decade in technical and management positions. As a member of the SMP server project at SUN Microsystem, he co-invented the industry’s first hardware testbench language, Vera, which is a part of today’s industry standard SystemVerilog. 

Eugene holds a Master of Science in Computer Engineering from Syracuse University, and a Bachelor and Master of Science in Electronic Engineering from Tsinghua University, Beijing.